I. Field of the Disclosure
The technology of the disclosure relates generally to metal-oxide semiconductor (MOS) field-effect transistors (MOSFETs), and particular to MOSFETs used as programmable switching devices, such as in memory cells.
II. Background
In modern computing systems, processors such as central processing units (CPUs) and digital signal processors (DSPs) process binary input signals based on a set of machine executable binary instructions and generate binary output signals as a result. To produce the expected results, processors must be able to accurately determine the state of an input signal (e.g., whether the input signal represents a binary zero or a binary one). The determinations are usually based on detecting a voltage level of the input signal and are carried out by logic gates. These logic gates may consist of various metal-oxide semiconductor (MOS) field-effect transistors (MOSFETs) arranged in a manner as to provide the desired logic operation. A MOSFET may be an n-channel MOSFET (nMOSFET) or a p-channel MOSFET (pMOSFET) depending on substrate materials.
In this regard, FIG. 1 illustrates an exemplary nMOSFET 10 that may be included in a logic gate. The nMOSFET 10 comprises a metal gate (MG) 12, an n-type source region 14, an n-type drain region 16, and a p-type substrate (P-sub) (body) 18. A high-k (HK) dielectric layer/interface layer 20 is disposed between the metal gate 12 and the body 18. The metal gate 12, the n-type source region 14, and the n-type drain region 16 are coupled to a gate (G) electrode 22, a source (S) electrode 24, and a drain (D) electrode 26, respectively.
With continuing reference to FIG. 1, a gate voltage (VG) 28 and a source voltage (VS) 30 provide a switching voltage (VGS) 32 that controls whether the nMOSFET 10 is in a depletion mode or an inversion mode. If the switching voltage (VGS) 32 is less than a threshold voltage (VT) of the nMOSFET 10, the nMOSFET 10 is in the depletion mode regardless of a drain voltage (VD) 34. When the nMOSFET 10 is in the depletion mode, a channel region 36 between the n-type source region 14 and the n-type drain region 16 becomes highly resistive. As a result, no electrical current flows between the n-type source region 14 and the n-type drain region 16. When the switching voltage (VGS) 32 is greater than or equal to the threshold voltage (VT) of the nMOSFET 10, the nMOSFET 10 switches into an inversion mode, and the channel region 36 becomes conductive. In the inversion mode, if a drain-to-source voltage (VDS) 38 is applied between the drain (D) electrode 26 and the source (S) electrode 24, electrons 40 are drawn to the n-type drain region 16 from the n-type source region 14, thus generating a drain current (ID) 42 flowing from the n-type drain region 16 to the n-type source region 14.